Various questions regarding SSD

[idata]

What is the best raid stripe size for the X25-E and X-25-M?

Will the existing line of Intel SSD's be compatible with Windows 7 TRIM command? If so when is this likely to happen?

If TRIM is going to be supported will it be supported via RAID?

Is there any update on the new 34nm SSD product line? When will specs be available?

Will the 34nm technology use the same controller or will it be a new controller?

EDIT:

I can now answer part of my own question. After extensive testing with IOmeter I have concluded that a 128k stripe size is going to work best for raid 0 in the vast majority of cases, and certainly for normal OS use. That is based on test results using two different controllers and stripe sizes ranging between 16k & 1042k. (Tests on one controller were limited to 256k due to limitations of the controller.) This involved a lot of work, for something that could easily have been explained.

Intel....

you are currently dealing with enthusiasts in your new SSD market, who are interested in the technology and want to know as much as possible about it. Why have the anonymous corporate attitude to your new and exciting product line? Why is there the party line of saying nothing about such an exciting product? (Even something as basic as letting people know they should be using AHCI and not IDE mode).MS seemed to have learnt that this is not the way to go with all the fantastic work they have done with Windows 7. Enthusiasts are raving about Windows 7 and that is going to really help Windows 7 launch to the mainstream with maximum impact.

Every now and then it is good to throw your (loyal) dog a bone 😉

/message/14887# 14887 Various questions regarding SSD

[idata]

I'm not an expert on SSD any more than most of you, but I do know that internally, SSD drives use a flash-like technology on chips, not platters like HDDs. These chips use fixed-size addressable pages to read/write data. SSDs must read/write very specific page-sizes somewhat like sectors on HDDs, but not exactly. For example, if you write only 2K of data, the SSD would actually need to read a 128K page of data, make changes to the data in RAM/cache, clear the original 128K page of data, then re-write 128K of data. This might be why you see gains and specific sizes of striping. I cannot speak as to what page sizes are optimal for the Intel SSDs, but perhaps you've discovered it. If you're striping is smaller (say, 4K), then it must repeat this procedure multiple times for the same 128K page because you've taken perhaps 64K of data and broken into 8 write operations. Does this make sense?

Reference: http://www.anandtech.com/printarticle.aspx?i=3531 http://www.anandtech.com/printarticle.aspx?i=3531

[idata]

Hi tingshen,

I have two x25-e's on a 5405. Your atto benchmark is seriously out of tilt. I can hit 500mb/sec with my set up. You can find reviews as linked below, which should give you a better idea of what you should be able to achieve.

http://www.areca.com.tw/products/pcie341.htm http://www.areca.com.tw/products/pcie341.htm (check out the pdf download in relative resource box)

http://it.anandtech.com/IT/showdoc.aspx?i=3532&p=1 http://it.anandtech.com/IT/showdoc.aspx?i=3532&p=1

http://techreport.com/articles.x/16291/1 http://techreport.com/articles.x/16291/1

[idata]

Hi redux,

do you get to see any official validation document from Areca regarding their range of products against X25-E & X25-M? I can easily find it in Adaptec website but not Areca

[idata]

Hi zulishk,

I read that the x25's have a 128k erase block, however there is also a statement from Winslow (Intel) that states "We've figured out a way to program and erase just what is necessary (in small bytes rather than large blocks) so our drive has tremendous efficiency for the life of the computing environment." Maybe that is a reference to the 128k erase block size rather than the 512k erase block size on other ssd's or maybe less than 128k gets erased. Only Intel knows.

Write combining may also be a factor and also the cache on hard raid may be a factor.

Interesting on two of the reviews I linked above a 64k strip was used.

I've also read someone stating on another forum that a 16K strip worked best for them using 2 X25-m's, but I find that hard to believe.

If the erase block size is 128k it would seem logical that a small strip size (on a full drive) would be a lot slower whilst also significantly increasing the erase cell count.

From my own testing with IOmeter this seemed to be the case as small strip sizes decreased speed but increased cpu usage (i.e. more work for less benefit.)

Considering the potential that the wrong strip size might be significantly increasing erase counts it's a shame Intel can't help shed a little light on this issue.

[idata]

Hi tingshen,

Yes, if go to the link ( http://www.areca.com.tw/products/pcie341.htm http://www.areca.com.tw/products/pcie341.htm ) look at the right hand side from "Relatived Resource" Look for the ARC1231ML with Intel SDD HDDs pdf at the bottom with the "new" flashing icon.