Definitions for Events

[mc7]

I have 730 Sata and 530 mSata SSDs.

When I check the smart logs

(sudo smartctl --log=devstat /dev/sdx),

the 730 seem to be giving me high

. Number of Hardware Resets

. Number of ASR Events

and the 530 mSata high

. Resets Between Cmd Acceptance and Completion

But what do these mean?

-What is and what causes "Resets Between Cmd Acceptance and Completion?"

-What are and what cause "ASR Events?"

Have searched in vain for definitions

(and maybe even reasonable bounds).

[mc7]

@joe_intel - thanks for those definitions.

I understand they are device statistics.

And thanks for the document linked, though it does not provide any clarification on normal values.

As for what they mean, I think the

Resets Between Command Acceptance and Command Completion on the mSata 530 seem ok,

as it equals the Number of Hardware Resets

and is probably related to the inability of the power-on self-test to complete becs it gets interrupted by real work,

as mentioned here

https://communities.intel.com/thread/48469 https://communities.intel.com/thread/48469

That leaves the high Number of Hardware Resets and Number of ASR Events on the Sata 730 SSD to think about.

While there are is only 1 Power-On reset daily,

there are about 10+ Hardware Resets and 3-5 ASR Events daily.

What causes an SSD Hardware Reset, besides a reboot or 'hot-plug'.

Any thoughts on what is behind these Hardware Resets and ASR Events?

[Kevin_M_Intel]

Hi alienheartbeat,

I can confirm that going into Hibernate will cause ASR Events to increase and Number of Hardware Resets to increase by 2. You can confirm this by checking the SMARTCTL output before and after going into Hibernate mode.

Kevin M

[mc7]

thanks Kevin, that makes snese.

However, the last time I hibernated one of my machines was about 2006, just to test it,

Did not seem a useful facility.

I also rarely (about 1/month) put them to sleep.

I shut down about once a day, and maybe reboot about once a day.