topic Re: Definitions for Events in Solid State Drives (NAND)

Definitions for Events

mc7 — Mon, 28 Jul 2014 10:37:17 GMT

I have 730 Sata and 530 mSata SSDs.

When I check the smart logs

(sudo smartctl --log=devstat /dev/sdx),

the 730 seem to be giving me high

. Number of Hardware Resets

. Number of ASR Events

and the 530 mSata high

. Resets Between Cmd Acceptance and Completion

But what do these mean?

-What is and what causes "Resets Between Cmd Acceptance and Completion?"

-What are and what cause "ASR Events?"

Have searched in vain for definitions

(and maybe even reasonable bounds).

Re: Definitions for Events

Kevin_M_Intel — Tue, 29 Jul 2014 14:49:09 GMT

Hi alienheartbeat,

I am sorry you are having problems.

I regret to say Linux is not my strength. I would recommend you checking on Linux communities or maybe a Linux experience member from our community can provide some feedback on this.

Kevin M

Re: Definitions for Events

Jose_H_Intel1 — Tue, 29 Jul 2014 21:18:46 GMT

Alienheartbeat, is it possible to share a screenshot of the SMART log showing these events?

Please share more information about your system, such as http://www.intel.com/support/siu.htm Intel® System Identification Utility or msinfo32 report (press Windows* key + R key, type "msinfo32", press OK and then File, Export). You can attach it with the Advanced Editor.

Re: Definitions for Events

mc7 — Wed, 30 Jul 2014 10:59:58 GMT

@kevin_intel No Linux problem here - I am asking about the meaning of Smart events in the context of Intel SSDs.

@joe_intel I have attached as requested:

. the logs for sda and sdb (devstat-sdx-140730.lst)

. the full smart listing for these two devices (fulllist-sdx-140730.lst)

. A system information report done with hardInfo (I don't use Windows so can't use your utility).

If you require any further info about the system let me know.

fwiw for the mSata 530, I notice that the number of

Resets Between Cmd Acceptance and Completion

is the same as the number of

Number of Hardware Resets

and I suspect this is related to the line in the 'capabilities' section:

Abort Offline collection upon new command,

an issue which has been raised elsewhere in these forums.

Please let me know if you need any further information.

Re: Definitions for Events

Jose_H_Intel1 — Thu, 31 Jul 2014 21:31:28 GMT

Alienheartbeat, I was able to find some information for you.

These "events" are actually Device Statistics as explained in the page 23, table 14 of the specifications document.

http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ssd-530-m2-specification.pdf http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/ssd-530-m2-specification.pdf

These three statistics do not have an equivalent SMART attribute but are explained below.

ASR = Asynchronous Signal Recovery. An ASR event is recorded when the device recovers from a loss of signal or when communication is established after hot plug.
The Number of Resets Between Command Acceptance and Command Completion statistic is a counter that records the number of Software Reset or Hardware Reset events that occur when one or more commands have been accepted by the device but have not reached command completion.
The Number of Hardware Resets statistic is the number of hardware resets RECEIVED by the device. This means the reset came from the PC or laptop.

None of these indicate an issue with the Intel® SSD. They are events that happen in the normal course of operation. The one exception might be ASR events. Steadily increasing ASR events might indicate an issue with the SATA port or the SATA cable.

Re: Definitions for Events

mc7 — Sat, 02 Aug 2014 07:38:56 GMT

@joe_intel - thanks for those definitions.

I understand they are device statistics.

And thanks for the document linked, though it does not provide any clarification on normal values.

As for what they mean, I think the

Resets Between Command Acceptance and Command Completion on the mSata 530 seem ok,

as it equals the Number of Hardware Resets

and is probably related to the inability of the power-on self-test to complete becs it gets interrupted by real work,

as mentioned here

https://communities.intel.com/thread/48469 https://communities.intel.com/thread/48469

That leaves the high Number of Hardware Resets and Number of ASR Events on the Sata 730 SSD to think about.

While there are is only 1 Power-On reset daily,

there are about 10+ Hardware Resets and 3-5 ASR Events daily.

What causes an SSD Hardware Reset, besides a reboot or 'hot-plug'.

Any thoughts on what is behind these Hardware Resets and ASR Events?

Re: Definitions for Events

Kevin_M_Intel — Tue, 05 Aug 2014 14:16:21 GMT

Hi alienheartbeat,

I can confirm that going into Hibernate will cause ASR Events to increase and Number of Hardware Resets to increase by 2. You can confirm this by checking the SMARTCTL output before and after going into Hibernate mode.

Kevin M

Re: Definitions for Events

mc7 — Fri, 08 Aug 2014 09:50:44 GMT

thanks Kevin, that makes snese.

However, the last time I hibernated one of my machines was about 2006, just to test it,

Did not seem a useful facility.

I also rarely (about 1/month) put them to sleep.

I shut down about once a day, and maybe reboot about once a day.