<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: X25-E Concurrent Writes in Archive</title>
    <link>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7882#M7311</link>
    <description>&lt;P&gt;Would it not depend on queue depth? Performance scaling stops after QD32. &lt;/P&gt;</description>
    <pubDate>Tue, 22 Feb 2011 09:02:36 GMT</pubDate>
    <dc:creator>idata</dc:creator>
    <dc:date>2011-02-22T09:02:36Z</dc:date>
    <item>
      <title>X25-E Concurrent Writes</title>
      <link>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7880#M7309</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We have a short questions about the internal concurreny of writes:&lt;/P&gt;&lt;P&gt;It is said that Native Command Queuing enables up to 32 concurrent operations, but how many (internal) operations can actually write concurrently.&lt;/P&gt;&lt;P&gt;In a normal HD I have x Read/Write Heads so (in theory) I could perform x concurrent operations on a physical level.&lt;/P&gt;&lt;P&gt;What is the theorectical and physical equivalent to this in the intel x25 e SSD&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;JS&lt;/P&gt;</description>
      <pubDate>Mon, 21 Feb 2011 23:30:57 GMT</pubDate>
      <guid>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7880#M7309</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2011-02-21T23:30:57Z</dc:date>
    </item>
    <item>
      <title>Re: X25-E Concurrent Writes</title>
      <link>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7881#M7310</link>
      <description>&lt;P&gt;The X25-E controller has 10 channels to 10 independent NAND chips so I would assume 10.&lt;/P&gt;</description>
      <pubDate>Tue, 22 Feb 2011 07:44:13 GMT</pubDate>
      <guid>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7881#M7310</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2011-02-22T07:44:13Z</dc:date>
    </item>
    <item>
      <title>Re: X25-E Concurrent Writes</title>
      <link>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7882#M7311</link>
      <description>&lt;P&gt;Would it not depend on queue depth? Performance scaling stops after QD32. &lt;/P&gt;</description>
      <pubDate>Tue, 22 Feb 2011 09:02:36 GMT</pubDate>
      <guid>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7882#M7311</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2011-02-22T09:02:36Z</dc:date>
    </item>
    <item>
      <title>Re: X25-E Concurrent Writes</title>
      <link>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7883#M7312</link>
      <description>&lt;P&gt;If we are talking about concurrent as in how many operations can be performed in a clock cycle...  I would guess 10 possible operations possible.  If using toggle or double data rate NAND, it would be 20 possible operations in a clock cycle.  This is my guessing based on what is public about the drive and assuming the clock is synchronous.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I guess it depends on how the question is framed.... Like how many IOPs do SSDs achieve in sequential reads at different QDs?  That would be a different answer...&lt;/P&gt;</description>
      <pubDate>Tue, 22 Feb 2011 21:02:52 GMT</pubDate>
      <guid>https://community.solidigm.com/t5/archive/x25-e-concurrent-writes/m-p/7883#M7312</guid>
      <dc:creator>idata</dc:creator>
      <dc:date>2011-02-22T21:02:52Z</dc:date>
    </item>
  </channel>
</rss>

